Mitigation of long wake-up delay of a crystal oscillator

ABSTRACT

An electronic circuit includes a first oscillator, a second oscillator and ancillary circuitry. The first oscillator is configured to generate a first clock signal and has a first wake-up delay. The second oscillator is configured to generate a second clock signal and has a second wake-up delay that is shorter than the first wake-up delay. The ancillary circuitry is configured to provide the second clock signal as an output clock signal during wake-up of the first oscillator, and, following the first wake-up delay, to provide the first clock signal as the output clock signal.

FIELD OF THE INVENTION

The present invention relates generally to oscillator circuits, andparticularly to methods and systems for mitigating wake-up delays ofcrystal oscillators.

BACKGROUND OF THE INVENTION

Crystal oscillators are used in various applications, such as forgenerating accurate clock signals in various types of electronicequipment.

Although accurate, some crystal oscillators, often low-poweroscillators, are characterized by slow wake-up.

SUMMARY OF THE INVENTION

An embodiment of the present invention that is described herein providesan electronic circuit including a first oscillator, a second oscillatorand ancillary circuitry. The first oscillator is configured to generatea first clock signal and has a first wake-up delay. The secondoscillator is configured to generate a second clock signal and has asecond wake-up delay that is shorter than the first wake-up delay. Theancillary circuitry is configured to provide the second clock signal asan output clock signal during wake-up of the first oscillator, and,following the first wake-up delay, to provide the first clock signal asthe output clock signal.

In some embodiments, the first oscillator has a first accuracy, and thesecond oscillator has a second accuracy that is poorer than the firstaccuracy. In some embodiments, the first oscillator includes a crystaloscillator, and the second oscillator includes a free-runningoscillator.

In a disclosed embodiment, the ancillary circuitry includes amultiplexer, configured to switch either the first clock signal or thesecond clock signal to an output over which the output clock signal isprovided, and a counter, configured to count a predefined delay and,upon expiry of the predefined delay, to switch the multiplexer fromoutputting the second clock signal to outputting the first clock signal.

In an alternative embodiment, the ancillary circuitry includes amultiplexer, configured to switch either the first clock signal or thesecond clock signal to an output over which the output clock signal isprovided, and a detector circuit, configured to switch the multiplexerfrom outputting the second clock signal to outputting the first clocksignal in response to detecting that the crystal oscillator reached apredefined expected performance.

In an embodiment, the second oscillator or the ancillary circuitry isconfigured to disable the second oscillator after starting to providethe first clock signal as the output clock signal.

There is additionally provided, in accordance with an embodiment of thepresent invention, a method for clock generation. The method includesgenerating a first clock signal by a first oscillator having a firstwake-up delay, and generating a second clock signal by a secondoscillator, which has a second wake-up delay that is shorter than thefirst wake-up delay. The second clock signal is provided as an outputclock signal during wake-up of the first oscillator, and the first clocksignal is provided as the output clock signal following the firstwake-up delay.

There is also provided, in accordance with an embodiment of the presentinvention, an electronic apparatus including electronic circuitry andclock generation circuitry. The electronic circuitry is clocked by aclock signal. The clock generation circuitry includes a firstoscillator, a second oscillator and ancillary circuitry. The firstoscillator is configured to generate a first clock signal and has afirst wake-up delay. The second oscillator is configured to generate asecond clock signal and has a second wake-up delay that is shorter thanthe first wake-up delay. The ancillary circuitry is configured to clockthe electronic circuitry with the second clock signal during wake-up ofthe first oscillator, and, following the first wake-up delay, to clockthe electronic circuitry with the first clock signal.

The present invention will be more fully understood from the followingdetailed description of the embodiments thereof, taken together with thedrawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram that schematically illustrates an IntegratedCircuit (IC) comprising fast wake-up clock generation circuitry, inaccordance with an embodiment of the present invention;

FIG. 2 is a flow chart that schematically illustrates a method for fastgeneration of a clock signal, in accordance with an embodiment of thepresent invention; and

FIG. 3 is a circuit diagram of a clock multiplexer, in accordance withan example embodiment of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS Overview

Embodiments of the present invention that are described herein provideimproved methods and systems for mitigating the relatively long wake-updelays of crystal oscillators. The disclosed techniques can be used, forexample, for generating a clock signal in a mobile computing device, orin any other application that calls for a clock signal that is bothaccurate and fast-waking. Typically although not necessarily, suchapplications tend to be low-power applications.

In some embodiments, an output clock signal is generated by clockgeneration circuitry. The clock generation circuitry comprises a crystaloscillator, a free-running oscillator, and ancillary circuitry. Thefree-running oscillator is typically less accurate than the crystaloscillator, but on the other hand has a considerably shorter wake-updelay.

In some embodiments, although not necessarily, the free-runningoscillator may be smaller in size than the crystal oscillator, and/orconsume less power. In some embodiments, the free-running oscillator maybe implemented entirely inside the device that uses the clock signal(e.g., a silicon IC), whereas the crystal oscillator may be implementedat least partially outside the device and therefore require dedicateddevice pins and external components such as a crystal, capacitors and/orresistors.

In some embodiments, both the crystal oscillator and the free-runningoscillator are started at power-up. In addition, a counter in theancillary circuitry starts counting a predefined delay. The counter istypically clocked by the free-running oscillator. Initially, before thecounter expires, the ancillary circuitry provides the output of thefree-running oscillator as the output clock signal. After the counterexpires, the ancillary circuitry starts providing the output of thecrystal oscillator as an output clock signal.

For example, the ancillary circuitry may comprise a multiplexer thatselects, depending on the counter status, either the output of thecrystal oscillator or the output of the free-running oscillator. Thepredefined delay counted by the counter is typically set to be at leastthe worst-case wake-up delay of the crystal oscillator. As such, whenthe counter expires, the crystal oscillator can be safely used as astable, valid clock signal. An optional variation of self-disabling thefree-running oscillator after switch-over to the crystal oscillator isalso described.

System Description

FIG. 1 is a block diagram that schematically illustrates an IntegratedCircuit (IC) 20 comprising fast wake-up clock generation circuitry, inaccordance with an embodiment of the present invention. In the presentexample, IC 20 is part of a mobile or laptop computer. In alternativeembodiments, the disclosed clock generation schemes can be used in anyother suitable kind of electronic equipment.

In the embodiment of FIG. 1, the clock generation circuitry in IC 20comprises a crystal oscillator 24, a free-running oscillator 28, andancillary circuitry that comprises a multiplexer (MUX) 32, a timecounter 36 and (optionally) a control module 40. MUX 32 receives theoutputs of crystal oscillator 24 and of free-running oscillator 28 asinputs, and selectably outputs one of them. The clock signal at theoutput of MUX 32 is referred to as an output clock signal produced bythe clock generation circuitry. MUX 32 is controlled by counter 36 (orat least depending on the expired/not-expired status of counter 36).

Crystal oscillator 24 is regarded as a primary oscillator, and it isused for producing the output clock signal under normal, steady-stateconditions. Crystal oscillator 24 is typically highly accurate, e.g., onthe order of several tens of parts-per-million (ppm). Crystal oscillator24 typically has a long wake-up delay. In an example embodiment, thewake-up delay of crystal oscillator 24 is on the order of severalhundred milliseconds.

In some embodiments, the clock generation circuitry uses free-runningoscillator 28 for generating the output clock signal during the longwake-up delay of crystal oscillator 24. Oscillator 28 is thus alsoreferred to as a secondary oscillator. Free-running oscillator 28 istypically much less accurate than crystal oscillator 24, e.g., on theorder of 2-3% when calibrated over temperature and process variations,or several tens of % without calibration. Typically, a device that iscalibrated during manufacturing will only be calibrated to compensatefor process variations. A temperature compensation circuit may reducevariations over temperature.

Although less accurate, the wake-up delay of free-running oscillator 28is significantly shorter than the wake-up delay of crystal oscillator24. In some embodiments, free-running oscillator 28 produces a validclock signal virtually immediately after it is started (e.g., uponpower-up or reset). In other embodiments, the free-running oscillatorhas a short wake-up delay on the order of several microseconds or less.

In various embodiments, free-running oscillator 28 may comprise, forexample, a Resistance-Capacitance (RC) oscillator, a ring oscillator, orany other suitable oscillator type.

In the context of the present patent application and in the claims, theterm “accuracy” of an oscillator (oscillator 24 or oscillator 28) mayrefer to the absolute long-term frequency accuracy, short-term jitter orwander, phase noise, and/or any other suitable measure relating tofrequency accuracy.

In the context of the present patent application and in the claims, theterm “wake-up delay” of an oscillator (oscillator 24 or oscillator 28)is defined as the delay from the time the oscillator is started (e.g.,from power-up or reset) until the clock signal produced by theoscillator meets its specified performance. The specified performancemay relate, for example, to amplitude, frequency accuracy, stability,spectral purity, or any other suitable performance measure.

The configuration of the clock generation circuitry shown in FIG. 1 isan example configuration that is depicted purely for the sake ofconceptual clarity. In alternative embodiments, any other suitableconfiguration can be used. For example, instead of counter 36, the clockgeneration circuitry may comprise a detector circuit that verifies theperformance of crystal oscillator 24 and detects whether the crystaloscillator reached some predefined expected performance. The expectedperformance may comprise a target amplitude of the clock signal, or anyother suitable parameter that indicates the crystal oscillator completedits stabilization process. In these embodiments, the detector circuitcontrols MUX 32, e.g., switches-over from free-running oscillator 28 tocrystal oscillator 24 in response to detecting that the crystaloscillator reached the predefined expected performance. Using a detectorcircuit instead of a counter may achieve earlier switch-over, since itdepends on the actual performance of the crystal oscillator and not onworst-case performance.

Typically, crystal oscillator 24 and free-running oscillator 28 generateclock signals having the same frequency. Alternatively, however, the twooscillators may generate clock signals having different frequencies. Insuch embodiments, the ancillary circuitry comprises one or morefrequency dividers or multipliers that match the frequencies of the twoclock signals as they arrive at MUX 32.

In various embodiments, the different elements of the clock generationcircuitry may be implemented using any suitable hardware, such as in anApplication-Specific Integrated Circuit (ASIC) or Field-ProgrammableGate Array (FPGA).

Mitigation of Crystal-Oscillator Wake-Up Delay Using Free-RunningOscillator

FIG. 2 is a flow chart that schematically illustrates a method for fastgeneration of a clock signal, in accordance with an embodiment of thepresent invention. The method begins at power-up of IC 20, or partthereof. Initially, by default, MUX 32 is set to provide the output offree-running oscillator 28 as the output clock signal.

Three events are triggered, typically simultaneously, at power-up:Free-running oscillator 28 starts operating, at a secondary oscillatorstart-up step 50. Crystal oscillator 24 starts operating, at a primaryoscillator start-up step 54. Counter 36 starts counting, at a counterstart-up step 58.

Following step 50, a valid output clock signal appears virtuallyimmediately at the output of MUX 32. At this stage the output clocksignal is generated by free-running oscillator 28, and therefore hassomewhat degraded accuracy.

Counter 36 is configured to measure a predefined time delay. In someembodiments, the predefined delay is set to be at least the worst-casewake-up delay of crystal oscillator 24. The worst-case wake-up delaytypically considers the full range of operating conditions specified foroscillator 24, e.g., taken over the full voltage and temperature range.In addition, the worst-case wake-up delay may also considermanufacturing process variations from one crystal oscillator to another.If the wake-up delay of oscillator 24 is expected to deteriorate overits lifetime, this factor may also be taken into account. In addition, asuitable margin may be added. When the above factors are consideredcorrectly, it is guaranteed that when counter 26 expires, crustaloscillator 24 is stable and produces a valid and accurate clock signal.In alternative embodiments, however, the predefined delay can be set toany other suitable value.

In the present example, counter 36 counts the predefined delay using theclock signal generated by free-running oscillator 28 (since the outputof crystal oscillator 24 may not be dependable at this stage). In analternative embodiment, the counter may be clocked by crystal oscillator24, not by free-running oscillator 28. In such an embodiment, thecounter starts counting when the crystal oscillator starts oscillating,and counts a predefined number of cycles after which the crystaloscillator is known to stabilize under worst-case conditions.

At a counter checking step 62, counter 36 checks whether the predefineddelay has expired. When the predefined delay expires, at a switch-overstep 66, counter 36 switches MUX 32 to provide the output of crystaloscillator 24 as the output clock signal. From this point, the outputclock signal is produced by crystal oscillator 24, and is thereforehighly accurate.

In some embodiments, the switch-over of step 66 is designed such thatthe transition of the output clock signal from the free-runningoscillator to the crystal oscillator is seamless and introduces littleor no transient response. An example implementation of MUX 32 that meetsthis condition is shown in FIG. 3 below.

In some embodiments, certain functions described above may be performedby control module 40. The control module may, for example, startoscillators 24 and 28 upon power-up or reset, configured counter 36 withthe predefined delay, start counter 36, initialize MUX 32, and/or switchMUX 32 in response to expiry of counter 36. Alternatively, any or all ofthese functions may be performed by logic that is coupled to theoscillators, counter and/or MUX, or by any other element of theancillary circuitry.

In some embodiments, free-running oscillator 28 self-disables after step66, i.e., after switching over to take the output clock signal fromcrystal oscillator 24. This feature helps to reduce power consumption.Alternatively, disabling of free-running oscillator 28 may be performedby any element of the ancillary circuitry, e.g., by control module 40.

FIG. 3 is a circuit diagram of MUX 32, in accordance with an exampleembodiment of the present invention. The MUX of FIG. 3 accepts two clocksignals as inputs—The output of crystal oscillator 24 and the output offree-running oscillator 28. The circuit also accepts a SELECT signal(e.g., from counter 36) that instructs the circuit which clock signal toprovide as the OUTPUT CLOCK SIGNAL output. The MUX circuit of FIG. 3comprises four D-Flip-Flops (D-FF) 70, four AND gates 74, and an OR gate78.

Typically, all four FFs 70 have asynchronous reset inputs that areconnected to a reset signal, in order ensure the clock output defaultafter power-up. This feature is not shown in the figure, for clarity.

Assuming both clock signals are toggling during switch-over, andassuming the SELECT signal is by default “0” (i.e., selecting the outputof the free-running oscillator), switching-over the SELECT signal to “1”will cause the OUTPUT CLOCK SIGNAL to switch to the output of thecrystal oscillator seamlessly without any glitch.

Although the embodiments described herein mainly address a free-runningoscillator that operates in conjunction with a crystal oscillator, themethods and systems described herein can also be used in otherapplications, such as with various other suitable types of oscillators.In such alternative embodiments, the slow wake-up time of any kind ofoscillator (“primary oscillator”) can be mitigated by complementing itwith a faster-waking oscillator (“secondary oscillator”) that producesthe output clock signal during the wake-up time of the primaryoscillator.

It will thus be appreciated that the embodiments described above arecited by way of example, and that the present invention is not limitedto what has been particularly shown and described hereinabove. Rather,the scope of the present invention includes both combinations andsub-combinations of the various features described hereinabove, as wellas variations and modifications thereof which would occur to personsskilled in the art upon reading the foregoing description and which arenot disclosed in the prior art. Documents incorporated by reference inthe present patent application are to be considered an integral part ofthe application except that to the extent any terms are defined in theseincorporated documents in a manner that conflicts with the definitionsmade explicitly or implicitly in the present specification, only thedefinitions in the present specification should be considered.

The invention claimed is:
 1. An electronic circuit, comprising: a crystal oscillator, which is configured to generate a first clock signal and which has a first wake-up delay; a free-running oscillator, which is configured to generate a second clock signal and which has a second wake-up delay that is shorter than the first wake-up delay; and ancillary circuitry, which is configured to provide the second clock signal as an output clock signal during wake-up of the crystal oscillator, and, following the first wake-up delay, to provide the first clock signal as the output clock signal.
 2. The circuit according to claim 1, wherein the crystal oscillator has a first accuracy, and wherein the free-running oscillator has a second accuracy that is poorer than the first accuracy.
 3. The circuit according to claim 1, wherein the ancillary circuitry comprises: a multiplexer, configured to switch either the first clock signal or the second clock signal to an output over which the output clock signal is provided; and a counter, configured to count a predefined delay and, upon expiry of the predefined delay, to switch the multiplexer from outputting the second clock signal to outputting the first clock signal.
 4. The circuit according to claim 1, wherein the ancillary circuitry comprises: a multiplexer, configured to switch either the first clock signal or the second clock signal to an output over which the output clock signal is provided; and a detector circuit, configured to switch the multiplexer from outputting the second clock signal to outputting the first clock signal in response to detecting that the crystal oscillator reached a predefined expected performance.
 5. The circuit according to claim 1, wherein the free-running oscillator or the ancillary circuitry is configured to disable the free-running oscillator after starting to provide the first clock signal as the output clock signal.
 6. A method for clock generation, comprising: generating a first clock signal by a crystal oscillator, which has a first wake-up delay; generating a second clock signal by a free-running oscillator, which has a second wake-up delay that is shorter than the first wake-up delay; and providing the second clock signal as an output clock signal during wake-up of the crystal oscillator, and, following the first wake-up delay, providing the first clock signal as the output clock signal.
 7. The method according to claim 6, wherein the crystal oscillator has a first accuracy, and wherein the free-running oscillator has a second accuracy that is poorer than the first accuracy.
 8. The method according to claim 6, wherein providing the second clock signal and the first clock signal comprise counting a predefined delay and, upon expiry of the predefined delay, switching a multiplexer from outputting the second clock signal to outputting the first clock signal as the output clock signal.
 9. The method according to claim 6, wherein providing the second clock signal and the first clock signal comprise switching a multiplexer from outputting the second clock signal to outputting the first clock signal as the output clock signal in response to detecting that the crystal oscillator reached a predefined expected performance.
 10. The method according to claim 6, and comprising disabling the free-running oscillator after starting to provide the first clock signal as the output clock signal.
 11. An electronic apparatus, comprising: electronic circuitry, which is clocked by a clock signal; and clock generation circuitry, comprising: a crystal oscillator, which is configured to generate a first clock signal and which has a first wake-up delay; a free-running oscillator, which is configured to generate a second clock signal and which has a second wake-up delay that is shorter than the first wake-up delay; and ancillary circuitry, which is configured to clock the electronic circuitry with the second clock signal during wake-up of the crystal oscillator, and, following the first wake-up delay, to clock the electronic circuitry with the first clock signal.
 12. The apparatus according to claim 11, wherein the crystal oscillator has a first accuracy, and wherein the free-running oscillator has a second accuracy that is poorer than the first accuracy.
 13. The apparatus according to claim 11, wherein the ancillary circuitry comprises: a multiplexer, configured to switch either the first clock signal or the second clock signal to clock the electronic circuitry; and a counter, configured to count a predefined delay, and upon expiry of the predefined delay to switch the multiplexer from outputting the second clock signal to outputting the first clock signal.
 14. The apparatus according to claim 11, wherein the ancillary circuitry comprises: a multiplexer, configured to switch either the first clock signal or the second clock signal to clock the electronic circuitry; and a detector circuit, configured to switch the multiplexer from outputting the second clock signal to outputting the first clock signal in response to detecting that the crystal oscillator reached a predefined expected performance.
 15. The apparatus according to claim 11, wherein the free-running oscillator or the ancillary circuitry is configured to disable the free-running oscillator after starting to clock the electronic circuitry with the first clock signal. 